Basic HTML version of Foils prepared 17 November 98

Foil 55 Cray T3E Cache Performance

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox
Interesting Article from SC97 proceedings on T3E performance
1 Peak data transfer rates on the CRAY T3E-900
2 Type of access Latency Bandwidth
3 in CPU cycles [MB/s]
4 Dcache load 2 7200
5 Scache load 8-10 7200
6 Dcache or
7 Scache store -- 3600
8
9 These rates correspond to the maximum instruction issue rate of two loads per CPU cycle or one store per CPU cycle.
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