Basic HTML version of Foils prepared 17 November 98

Foil 66 Cache Coherent or Not?

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox
1 Suppose two processors cache the same variable stored in memory of one of the processors
2 One must ensure cache coherence so that when one cache value changes, all do!
3 ....
4 ....
5 System Interconnection Network
6 L3 Cache
7 Main
8 Memory
9 Main
10 Memory
11 Cached Value of same shared variable
12 Board level Interconnection Network
13 Board level Interconnection Network
in Table To:

© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Apr 11 1999