Basic HTML version of Foils prepared 17 November 98

Foil 61 SGI Origin II

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox
NPAC Summary of Origin 2000 Architecture
Also, each node has two primary caches (each 32KB two-way set-associative) and one secondary L2 cache (1 or 4MB two-way set associative) per CPU.
Each node has hardware cache coherency using a directory system and a maximum bandwidth of 780MB/sec.
The entire system (Cray Origin2000) has up to 512 such nodes, that is, up to 1024 processors.
  • For a 195-MHz R10000 processor, peak performance per processor is 390 MFLOPS or 780 MIPS (4 instructions per cycle), leading to an aggregate peak performance of almost 500 GFLOPS in a maximally sized machine.

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