Basic HTML version of Foils prepared 17 November 98

Foil 87 Interconnect / Communications System of Tera II

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox
Tera Architecture and System Links for Foil 87
A node has four ports (five if a resource is attached).
Each port simultaneously transmits and receives an entire 164-bit packet every 3 ns clock cycle.
Of the 164 bits, 64 are data, so the data bandwidth per port is 2.67 GB/s in each direction.
The network bisection bandwidth is 2.67p GB/s. (p is number of processors)
The network routing nodes contain no buffers other than those required for the pipeline.
  • Instead, all messages are immediately routed to an output port.

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