Basic HTML version of Foils prepared June 1996

Foil 18 The Overlooked Bandwidth

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 With modern DRAMs:
  • 1-16 GB/sec at the row buffers!
  • Even more for SRAMs!
2 Multiplexor
3 Row Buffer
4 Row Buffer
5 Multiple
6 internal
7 banks
8 256-4096 bits wide
9 select 1-9 bits: maybe 30-50 MB/s
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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