Basic HTML version of Foils prepared June 1996

Foil 36 Choosing the Processing Macro

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Today's "conventional wisdom:"
  • Complex memory hierarchy driving superscalar, superpipelined, branch predictions, fast TLBs, multiple function units, multi ported register files,.....
2 Does that make sense in PIM environment?
  • Large bandwidth from direct row buffer access
  • Reduced latency (no chip crossings)
  • Naturally closely coupled parallelism
3 Answer: No! Better choice: design for:
  • Maximum performance "per transistor"
  • Minimize power per mip
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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