Basic HTML version of Foils prepared June 1996

Foil 37 Performance Per Transistor

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
1 Performance data from uP vendors
2 Transistor count excludes on-chip caches
3 Performance normalized by clock rate
4 Conclusion: Simplest is best! (250K Transistor CPU)
5 Millions of Transistors (CPU)
6 Millions of Transistors (CPU)
7 Normalized SPECINTS
8 Normalized SPECFLTS
in Table To:

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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