Basic HTML version of Foils prepared June 1996
Foil 23 Current PIM Chips
From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
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Storage
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0.5 MB
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0.5 MB
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0.05 MB
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0.128 MB
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Chip
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EXECUBE
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AD SHARC
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TI MVP
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MIT MAP
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Terasys PIM
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First
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Silicon
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1993
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1994
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1994
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1996
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1993
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Peak
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50 Mips
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120 Mflops
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2000 Mops
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800 Mflops
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625 M bit
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ops
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0.016 MB
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MB/
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Perf.
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0.01
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MB/Mip
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0.005
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MB/MF
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0.000025
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MB/Mop
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0.00016
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MB/MF
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0.000026
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MB/bit op
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Organization
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16 bit
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SIMD/MIMD CMOS
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Single CPU and
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Memory
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1 CPU, 4 DSP's
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4 Superscalar
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CPU's
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1024
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16-bit ALU's
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Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu
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