Basic HTML version of Foils prepared June 1996

Foil 26 EXECUBE: The First High Density PIM

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
4 Mbit DRAM + 100K Gate base: 5V, 2.7W
Single part type: NO GLUE!
SIMD & MIMD - In Any Combination
Huge increase in BW, pins, silicon.. utilization
register
instruction
register
register
array
register
32Kx9 DRAM
macro
32Kx9 DRAM
macro
ALU
SIMD
MIMD
mode
SIMD
Broadcast Bus
decode
logic
DMA
logic

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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