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LOCAL foilset Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing

This was part of a set of PAWS 96(Mandalay Beach) Presentations

Kogge and Collaboraters describe PIM as an emerging architecture where logic and memory combined on same chip which increases memory bandwidth naturally

Conventional Architectures tend to waste transistors measured in terms silicon used per unit operation

Both Existing designs and projections to PetaFlop timescale(2007) are given

Table of Contents for Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing

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Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu