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Hardware may handle only single hop, or multiple hops as in routing chips on Paragon.
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| 2 |
Software may mask hardware limitations so one sees full connectivity even if physically limited. Note that multiple hops always leads to poorer latency as this is travel time per bit. However we can keep bandwidth high even with multiple hops by increasing "size" of channels e.g. transmitting several bits simultaneously. Software can hide
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Latency by pipelining -- doing other thing while bits in transit. This is circuit switching if done at low level.
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Partial connectivity by supplying software layer that handles routing -- this is familiar on Internet
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| 3 |
Latency related to graph diameter, among many other factors
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Graph may also represent calculations that need to be performed, and the information exchange required.
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