Basic HTML version of Foils prepared 21 October 1995

Foil 32 SIMD (Single Instruction Multiple Data) Architecture

From New CPS615 Foils-- B 28 August 95 CPS615 Basic Simulation Track for Computational Science -- Fall Semester 95. by Geoffrey C. Fox
1 CM2 - 64 K processors with 1 bit arithmetic - hypercube network, broadcast network can also combine , "global or" network
2 Maspar, DECmpp - 16 K processors with 4 bit (MP-1), 32 bit (MP-2) arithmetic, two-dimensional mesh and general switch
3 Execube - 16 bit processors with 8 integrated into IBM 4 mbit memory chip, SIMD or MIMD or both,
4 512 processors on IBM RS6000 with three dimensional mesh
in Table To:

© on Tue Oct 7 1997