Basic HTML version of Foils prepared 21 October 1995

Foil 67 Characteristics of INTEL i860 Compute Node

From New CPS615 Foils-- B 28 August 95 CPS615 Basic Simulation Track for Computational Science -- Fall Semester 95. by Geoffrey C. Fox


RISC engine + 2FPUs + graphics accelerator
40 MHz clock
Parallel integer and floating-point processing units
Parallel multiplier and adder units within floating-point unit
Pipelined floating-point processing units (3-stage pipe)
80 MFlops (SP) Peak, 60 MFlops (DP) Peak, 33 MIP's (Integer)
all transcendental functions done in software
16 MBytes Main Memory (expandable to 64 MBytes)
160 MBytes/sec peak DRAM access rate
Very hard to build good compilers for i860!



© on Tue Oct 7 1997