HTML version of Scripted Foils prepared 27 August 1996

Foil 77 64 Node nCUBE Board

From CPS615-Introduction-Course,Driving Technology and HPCC Current Status and Futures CPS615 Basic Simulation Track for Computational Science -- Fall Semester 96. by Geoffrey C. Fox *
Secs 34
1 Each node is CPU and 6 memory chips -- CPU Chip integrates communication channels with floating, integer and logical CPU functions
in Table To:

© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Wed Aug 27 1997