Scripted HTML version of Foils prepared 18 Sept 1995

Foil 64 SIMD (Single Instruction Multiple Data) Architecture

From Second set of lectures on CPS615 Parallel Computing Overview CPS615 Basic Simulation Track for Computational Science -- Fall Semester 95. by Geoffrey C. Fox *
CM2 - 64 K processors with 1 bit arithmetic - hypercube network, broadcast network can also combine , "global or" network
Maspar, DECmpp - 16 K processors with 4 bit (MP-1), 32 bit (MP-2) arithmetic, two-dimensional mesh and general switch
Execube - 16 bit processors with 8 integrated into IBM 4 mbit memory chip, SIMD or MIMD or both,
512 processors on IBM RS6000 with three dimensional mesh

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