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Foil 77 Category III Petaflop Design -- Processor in Memory (PIM)

From Second set of lectures on CPS615 Parallel Computing Overview CPS615 Basic Simulation Track for Computational Science -- Fall Semester 95. by Geoffrey C. Fox *
See Chapter 6 of Petaflops Report -- July 94
This design is an extrapolation of systems such as the J machine(Dally), Execube (Loral) or Mosaic(Seitz). It features CPU and memory integrated on the chip (PIM).
Unlike such systems today, in the year 2015 such PIM designs have substantial memory per processor

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