Scripted HTML version of Foils prepared April 27 97

Foil 6 Performance Per Transistor

From And the HPCN Future is: Petaflop Computers and Java and Web Technologies Aachen Parallel Computing Workshop, Pallas Presentation Germany -- April 21,23 97. by Geoffrey C. Fox *
Performance data from uP vendors
Transistor count excludes on-chip caches
Performance normalized by clock rate
Conclusion: Simplest is best! (250K Transistor CPU)
Millions of Transistors (CPU)
Millions of Transistors (CPU)
Normalized SPECINTS
Normalized SPECFLTS

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