Title and abstract for

Some Numerical Memory and MicroProcessor Projections for PetaFlops

Given by Peter Kogge Notre Dame at JNAC (PetaFlops) Presentation on August 28,1996. Foils prepared August 24 1996
which leads to edit sector initialized at overall parameters
which lists all addon files pointed to in foilset
This is a SINGLE file Containing all Foils in nonIMAGE (i.e. HTML) form
This contains all WebWisdom links preceded by those referenced in this foilset
This contains an Index of Foilset Suitable for Printing (There is no easy way of Printing all foils -- just the index)
This just contains Title of Foilset and Links
This was part of a set of PetaFlop (JNAC) Presentations to group of Federal Program Managers
JNAC = Joint National Advanced Computing Initiative
This uses Moore's Law Projections of Technology for Logic and Memory
and uses Bodega Bay Application Analysis to cost memory for a "realistic" machine
Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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