Basic HTML version of Foils prepared 17 November 98

Foil 5 Architectural Trends

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox


1 Greatest trend in VLSI generation is increase in parallelism
  • Up to 1985: bit level parallelism: 4-bit -> 8 bit -> 16-bit
    • slows after 32 bit
    • adoption of 64-bit now under way, 128-bit far (not performance issue)
    • important inflection point when 32-bit microprocessor and cache fit on a chip
  • Mid 80s to mid 90s: instruction level parallelism
    • pipelining and simple instruction sets, + compiler advances (RISC)
    • on-chip caches and functional units => superscalar execution
    • greater sophistication: out of order execution, speculation, prediction
      • to deal with control transfer and latency problems
    • Next step: thread level parallelism

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