Basic HTML version of Foils prepared 17 November 98

Foil 55 Cray T3E Cache Performance

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox
Interesting Article from SC97 proceedings on T3E performance
Peak data transfer rates on the CRAY T3E-900
Type of access Latency Bandwidth
in CPU cycles [MB/s]
Dcache load 2 7200
Scache load 8-10 7200
Dcache or
Scache store -- 3600
These rates correspond to the maximum instruction issue rate of two loads per CPU cycle or one store per CPU cycle.

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