Basic HTML version of Foils prepared 17 November 98

Foil 66 Cache Coherent or Not?

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox
Suppose two processors cache the same variable stored in memory of one of the processors
One must ensure cache coherence so that when one cache value changes, all do!
....
....
System Interconnection Network
L3 Cache
Main
Memory
Main
Memory
Cached Value of same shared variable
Board level Interconnection Network
Board level Interconnection Network

© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Apr 11 1999