Basic HTML version of Foils prepared 17 November 98

Foil 81 Overview of the Tera MTA I

From Master Foilset for HPC Achitecture Overview CPS615 Introduction to Computational Science -- Fall Semester 1998. by Geoffrey C. Fox

Tera Architecture and System Links for Foil 81
Tera computer system is a shared memory multiprocessor.
  • From its specification, it also implements the true shared memory programming model for which the performance of the system does not depend on the placement of data in memory.
  • i.e. a true uniform memory system (UMA) whereas Sun E10000 is almost UMA and Origin 2000 NUMA
The Tera is a multi-processor which potentially can accommodate up to 256 processors.
  • The system runs stand-alone and requires no front end.
    • Network connection to workstations and other computer systems is accomplished via 32- or 64-bit HIPPI channels.
    • All data path widths are 64 bits, including the processor-network interface.
The clock speed is nominally 333 Mhz, giving each processor a data path bandwidth of one billion 64-bit results per second and a peak performance of one gigaflops.



© Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Sun Apr 11 1999