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The Tera Processors are multithreaded (called a stream) and each processor switches context every cycle among as many as 128 hardware threads, thereby hiding up to 128 cycles (384 ns) of memory latency.
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Each processor executes a 21 stage pipeline and so can have 21 separate streams executing simultaneously
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Each stream can issue as many as eight memory references without waiting for earlier ones to finish, further augmenting the memory latency tolerance of the processor.
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A stream implements a load-store architecture with three addressing modes and 31 general-purpose 64-bit registers.
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Switching between such streams ("threads") is fully supported by hardware
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The peak memory bandwidth is 2.67 gigabytes per second.
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