Basic HTML version of Foils prepared June 1996

Foil 18 The Overlooked Bandwidth

From Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing PAWS 96 Mandalay Beach -- April 21-26 1996. by Peter Kogge Notre Dame
With modern DRAMs:
  • 1-16 GB/sec at the row buffers!
  • Even more for SRAMs!
Multiplexor
Row Buffer
Row Buffer
Multiple
internal
banks
256-4096 bits wide
select 1-9 bits: maybe 30-50 MB/s

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

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