Basic Foilset Search HELP! * YELLOW=global GREY=local Full Index for

GLOBAL foilset HPCC Futures Topic 2:A Possible PetaFlop Initiative

Given by Geoffrey Fox, Peter Kogge at Trip to China on July 12-28,96. Foils prepared July 6 1996
More Detail! * Foil Index from this file * See also color IMAGE

This describes some aspects of a national study of the future of HPCC which started with a meeting in February 1994 at Pasadena
The SIA (Semiconductor Industry Association) projections are used to define feasible memory and CPU scenarios
We describe hardware architecture with Superconducting and PIM (Processor in Memory possibilities) for CPU and optics for interconnect
The Software situation is captured by notes from a working group at June 96 Bodega Bay meeting
The role of new algorithms is expected to be very important

This mixed presentation uses parts of the following base foilsets which can also be looked at on their own!
General Collection of Research Foils -- July--December 1996
Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing
Miscellaneous Presentation Material used in 1996
Master Foils for A Short Overview of HPCC -- From GigaFlops to PetaFlops and From Tightly Coupled MPP's to the World Wide Web
Master Set B of Overview Material on Parallel Computing for CPS615 Foils
Summary of Working Groups at PAWS and PetaSoft Meetings

Table of Contents for HPCC Futures Topic 2:A Possible PetaFlop Initiative

1 Separate IMAGE * Separate HTML Status of "Classic" HPCC -- June1996
Futures-2: Petaflops and Real Software in 2007?
2 Separate IMAGE * Separate HTML Abstract of HPCC Futures 2: PetaFlop in 2007!
3 Separate IMAGE * Separate HTML Petaflop Chain of Events
4 Separate IMAGE * Separate HTML Overall Remarks on the March to PetaFlops - I
5 Separate IMAGE * Separate HTML Overall Remarks on the March to PetaFlops - II
6 Separate IMAGE * Separate HTML Petaflop Performance for Flow in Porous Media?
7 Separate IMAGE * Separate HTML Target Flow in Porous Media Problem (Glimm - Petaflop Workshop)
8 Separate IMAGE * Separate HTML NASA's Projection of Memory and Computational Requirements upto Petaflops for Aerospace Applications
9 Separate IMAGE * Separate HTML Peak Supercomputer Performance
10 Separate IMAGE * Separate HTML Pasadena Architectures
11 Separate IMAGE * Separate HTML Chip Density Projections to year 2013
12 Separate IMAGE * Separate HTML Clock Speed and I/O Speed in megabytes/sec per pin through year 2013
13 Separate IMAGE * Separate HTML PetaFlops Applications
14 Separate IMAGE * Separate HTML Supercomputer Architectures in Years 2005-2010 -- I
15 Separate IMAGE * Separate HTML Supercomputer Architectures in Years 2005-2010 -- II
16 Separate IMAGE * Separate HTML Supercomputer Architectures in Years 2005-2010 -- III
17 Separate IMAGE * Separate HTML Current PIM Chips
18 Separate IMAGE * Separate HTML New "Strawman" PIM Processing Node Macro
19 Separate IMAGE * Separate HTML "Strawman" Chip Floorplan
20 Separate IMAGE * Separate HTML SIA-Based PIM Chip Projections
21 Separate IMAGE * Separate HTML Comparison of Supercomputer Architectures
22 Separate IMAGE * Separate HTML Algorithm and Software Challenges -- The Latency Agenda!
23 Separate IMAGE * Separate HTML Overall Suggestions -- I
24 Separate IMAGE * Separate HTML Overall Suggestions - II
25 Separate IMAGE * Separate HTML Other Suggested Point Designs
26 Separate IMAGE * Separate HTML Latency Research Is Needed
27 Separate IMAGE * Separate HTML Geometric Structure of Problems and Computers
28 Separate IMAGE * Separate HTML Memory Hierarchy versus Distribution
29 Separate IMAGE * Separate HTML Needed Algorithm/Application Evaluations
30 Separate IMAGE * Separate HTML Application Oriented Software Issues -- April 24,1996
31 Separate IMAGE * Separate HTML Language Related Issues
32 Separate IMAGE * Separate HTML Library and Tool Issues
33 Separate IMAGE * Separate HTML Operating System Issues - I
34 Separate IMAGE * Separate HTML Operating System Issues - II
35 Separate IMAGE * Separate HTML "Initial" Findings of the "Implementation" Subgroup at PetaSoft 96
36 Separate IMAGE * Separate HTML Initial Thoughts I
37 Separate IMAGE * Separate HTML Initial Thoughts II
38 Separate IMAGE * Separate HTML The MPI Program Execution Model
39 Separate IMAGE * Separate HTML The PetaSoft Program Execution Model
40 Separate IMAGE * Separate HTML Findings 1) and 2) -- Memory Hierarchy
41 Separate IMAGE * Separate HTML Findings 3) and 4) -- Using Memory Hierarchy
42 Separate IMAGE * Separate HTML Findings 5) and 6) -- Layered Software
43 Separate IMAGE * Separate HTML The Layered Software Model
44 Separate IMAGE * Separate HTML Some Examples of a Layered Software System
45 Separate IMAGE * Separate HTML Finding 7) Testbeds
46 Separate IMAGE * Separate HTML Findings 8) and 9) Applications
47 Separate IMAGE * Separate HTML Findings 10) to 14) General Points
Full WebWisdom URL and this Foilset Search
Alias List This contains all WebWisdom links preceded by those referenced in this foilset

List of WebWisdom URL's Used in this Foilset

Northeast Parallel Architectures Center, Syracuse University, npac@npac.syr.edu

If you have any comments about this server, send e-mail to webmaster@npac.syr.edu.

Page produced by wwwfoil on Tue Feb 18 1997