Table of Contents for Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing

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1 Processing-In-Memory (PIM) Architectures for Very High Performance MPP Computing
2 Acknowledgements
3 Memory & CPU Bandwidth Gap
4 Key Points
5 This Talk: A Better Way!
6 Observations on This Talk
7 HPCC & TeraFlops
8 Petaflop Chain of Events
9 Results from Pasadena `94
10 PetaFlops Applications
11 Pasadena Architectures
12 Bodega Bay: Primary Memory
13 Bodega Bay: Secondary Memory
14 Bodega Bay: Aggregate I/O
15 Cost Considerations: Processors
16 Cost Considerations: Memory
17 The "Hidden Costs" of Modern Systems
18 The Overlooked Bandwidth
19 Modern "Alternative" RAMs
20 Processing In Memory (PIM): Reclaiming the Bandwidth
21 PIM: Optimizing the System
22 Market Demand for Dense Processing
23 Current PIM Chips
24 Key Problem: Memory Density
25 Vendors with Known DRAM PIM Capability
26 EXECUBE: The First High Density PIM
27 Execube Processing Node
28 Tiling of Execube Processing Nodes
29 Lessons Learned from EXECUBE
30 New "Strawman" PIM Processing Node Macro
31 "Strawman" Chip Floorplan
32 Strawman Chip Interfaces
33 Strawman PIM Chip with I/O Macros
34 Strawman Properties
35 Strawman PIM "Memory Card"
36 Choosing the Processing Macro
37 Performance Per Transistor
38 SIA-Based PIM Chip Projections
39 Silicon Area for a Teraflop
40 Parallelism
41 Petaflop PIM System Size
42 Power Projections (Logic)
43 Power Per Sq. Cm
44 3D Stacking
45 Potential PIM Cube
46 Potential PIM Cube
47 Further Work: Hardware
48 Further Work:Algorithm Development
49 Further Work: Software Development
50 Current ND PIM Work In Progress
51 Conclusion

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